Synopsys Off Campus Drive 2023 for its Intern Technical-Engineering, Synopsys Drive is organizing Off CAmpus Drive for candidates in Any Batch. In order to apply, candidates should have degree in B.E/B.Tech/M.E/M.Tech Degree. if you are interested, Please apply as soon as possible.
Company Name: Synopsys
Role: Intern Technical-Engineering
Location: Hyderabad
Experience: Freshers
Qualification: B.E/B.Tech/M.E/M.Tech
Batch: Any Batch
Job Type: Full Time
Salary: Best in Industry
Synopsys Off Campus Drive 2023
About Synopsys:
- We are looking for an Intern (Technical Engineering) to join a growing, dynamic, and multi-cultural engineering team at the heart of a worldwide semiconductor CAD community.
- If your passion is to work in a challenging environment with a tremendous learning & growth potential, you can become one of us.
- Implementing innovative solutions for customer requirements, following existing procedures but have a critical perspective on what they are doing and can tradeoff the optimal with the best on a daily basis.
Job Description:
- In this role, you would be developing, troubleshooting, and debugging our cloud hosted platform. Work with senior designers and extend your contribution towards delivering a stable delivery.
- The ideal candidate will have sound knowledge on Java and database technologies.
- We are looking forward for leveraging your experience in topics such as micro services, Kubernetes and Cloud native applications.
Requirements:
- University degree in Electrical/Computers/Materials/Physics/Mechanics Engineering
- Good programming skills in at least one of the languages TCL, Python, Perl, bash
- Background knowledge of circuit theory
- Familiarity with physical verification flows like LVS/DRC
- Experience with UNIX/Linux environment
- Capability to produce adequate technical documentation
- Exceptional desire to learn, explore new technologies and demonstrate good investigation and problem-solving skills
- Good English communication skills
Key words: Layout, Physical Verification, Runset, LVS, DRC, ICV, ICVWB, Python, Tcl
Responsibility:
- Design, develop, troubleshoot or debug IC physical verification tools, runsets and flows for the development of integrated circuits.
- Providing help for Design Rule Check (DRC), Layout Versus Schematic (LVS), FILL runsets related issues for advanced processes.
- Should be able to read complex layout rules and layout structures.
- Creation and execution of QA test cases and regression suites including both schematic and layout entry.
- Help global layout design team by debugging flow, tool, runset and layout issues.
- Develop routines and utility programs to aid in verification of layout design.
- Build productive working relationships with cross functional teams.
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